A conventional approach to the fabrication of integrated Schottky transistor logic arrays is to fabricate a "master slice" logic array, including all active devices. Thereafter, the surface of the master slice is passivated by a passivation layer and stored pending programmation of the slice. The slice is custom-programmed by selectively opening vias to particular devices.
When emitter areas and other critical components are scaled down to one micrometer size, there is a problem in finding them under the passivation layer. Chances are therefore increased that a misalignment between the emitter via and the emitter contact surface will occur, in turn increasing the chance that a less-than-ideal connection will be made. It has therefore been unfeasible to passivate highly miniaturized master slices and store them for future, custom programmation steps. Instead, logic arrays having extremely small controlling dimensions must be custom programmed immediately without an intervening passivation step. If a passivating layer such as nitride or oxide is not deposited on the slice surface, non-programmed semiconductor devices present on the chip must be circumvented by the leads. This decreases routing channel flexibility.
Another problem associated with fabrication, passivation and later custom programmation of Schottky transistor logic arrays is inadequate passivation of the Schottky diodes. The Schottky diodes are generally formed by depositing a layer of metal next to a lightly doped area of semiconductor material. The type of metal deposited on the semiconductor material determines the height of the Schottky diode barrier. Platinum Silicide (PtSi) has a higher Schottky diode characteristic than aluminum, a typical contact metal. Where a high-barrier Schottky diode is desired to be fabricated, it is therefore important to prevent low barrier metal from circumventing the high-barrier metal Schottky contact pad. If established, a low barrier Schottky diode will dominate the operating characteristics of the diode junction.
In a conventional process, a first, high-barrier metal such as platinum, iridium or palladium is deposited in the Schottky diode contact. Where platinum is used, platinum silicide (PtSi) forms on contact. A premetal cleanup dip is then done before the deposition of the second metal. This dip can etch the oxide surrounding the first metal pad, exposing the underlying semiconductor. When a second metal such as aluminum or titanium/tungsten composite (Ti-W) is used as a lead to the device, filling the diode contact, the second metal may contact the semiconductor where the oxide has been etched.
Aluminum and Ti-W have lower barrier diode characteristics than PtSi. Any contact between them and the semiconductor will create a low-barrier diode that dominates or "shorts out" the high barrier PtSi diode. The risk of high barrier Schottky diode shortout decreases quality control of the finished slice.
Another problem associated with the decreasing size of integrated circuit emitters is emitter-collector short-out. In order to provide an ohmic contact with each active region of a semiconductor device, a contact region of highly doped material is provided. However, for proper formation of the space charge region, the emitter also needs to retain a less heavily doped, active region. As the entire emitter is scaled down in size, problems arise in separating the different dopant concentrations found in the emitter and emitter contact regions, so that the highly doped emitter contact region may spike through the base to the collector region. Since high concentrations of dopant increase conductivity, the emitter-collector junction is shorted out.
In view of the above problems, a need has arisen to develop a process for fabricating a Schottky transistor logic array having small dimensional size but enhanced quality control. A further need exists to provide a process whereby a Schottky transistor logic array may be stored in a passivated state pending custom programmation.